1. Field of the Invention
The present invention relates to photolithography equipment. More particularly, the present invention relates to photolithography equipment having an exposure apparatus and a wafer pre-alignment apparatus for aligning wafers with the optics of the exposure apparatus. The present invention also relates to a method of aligning wafers with the optics of the exposure apparatus of photolithography equipment.
2. Description of the Related Art
The fabricating of semiconductor devices includes a process of coating an upper surface of a wafer with photoresist (hereinafter, referred to “PR”) to form a layer of PR having a predetermined thickness on the wafer, a process of exposing the layer of PR to the image of a pattern such as a circuit pattern, a process of developing the exposed layer of PR to thereby pattern the layer of PR, and a process of etching the surface lying under the patterned layer of PR. As a result, a pattern, namely the circuit pattern, is formed on the wafer. The exposure process entails transmitting light onto the wafer through a reticle bearing a pattern corresponding to the desired pattern to be formed on the wafer. Accordingly, an image of the desired pattern is transferred to the wafer. Thus, in the exposure process, it is very important to align the wafer precisely with the reticle. Recently, 25 or 50 wafers are being fabricated by lot into the same type of memory device. For example, 100 wafers may be divided into four lots each according to a different type of memory device that is to be fabricated. Thus, the wafers of any one lot are all subjected to the same exposure process sequentially and selectively. Therefore, it is also important to align each wafer of the lot precisely with the optics of the exposure apparatus and, in particular, with the reticle so that the memory devices are not only of good quality but have uniform characteristics.
In general, the wafers are aligned in two stages. The first stage is a pre-alignment process in which a flat zone of the wafer is used to orient the wafer in a certain direction before the wafer is transferred to a wafer stage of the exposure apparatus. There, a desired pattern and an alignment mark are formed on the wafer using a first reticle (hereinafter, the pre-alignment will be referred to as the “first alignment process”). The second stage is an alignment process in which the wafer is aligned using the wafer stage and the alignment mark (hereinafter, referred to as the “second alignment process”) once the wafer has been transferred to the exposure apparatus. Subsequently, a desired circuit pattern is formed on the wafer using a reticle different from the first reticle.
An example of the first alignment process has been disclosed in Korean Patent Laid-Open Publication No. 2003-0087732 (laid-open on Nov. 5, 2003). This publication discloses a technique of checking the relative angular position of each wafer and compensating for deviations of the position from a desired position. However, completing the first alignment process using this technique for an entire lot or for several lots of wafers would require a great amount of time because the relative angular positions of the each of the wafers would have to be individually checked and adjusted, if necessary.
A conventional method of aligning wafers, when the wafers are grouped together in lots, is to use the first wafer subjected to the first alignment process as a reference wafer for all of the other wafers that are subsequently pre-aligned. More specifically, the pre-alignment unit detects the relative position of the flat zone of a first wafer loaded into the unit. The angle by which the first wafer is misaligned is calculated by a control unit based on the detected relative position of the flat zone. The calculated angle is stored as misalignment data in the control unit. The control unit then controls the pre-alignment unit based on the misalignment data to adjust the relative position of the first wafer so that the misalignment is compensated for.
In the conventional method, the reference misalignment data generated using the first wafer loaded into the pre-alignment unit is used as a reference angle. That is, this data is applied to the remaining wafers of the lot to pre-align the remaining wafers. However, not all of the wafers in a lot are transferred to the pre-alignment unit with exactly the same orientation. Thus, at least one or more wafers may be misaligned when the first alignment process is carried out using only the reference misalignment data to control the operation of the pre-alignment unit.
In this case, an alignment mark detection unit of the exposure apparatus fails to find the alignment mark on one or more of the wafers during the second alignment process. In this respect, FIG. 1A shows a wafer W that is transferred to the exposure apparatus after the first alignment process has been performed properly. That is, the flat zone FZ of the wafer W faces in a desired predetermined direction. In this case, the detection unit P immediately finds the alignment mark W1. Reference “A” denotes an imaginary grid that maps out the exposure regions or shots of the wafer W. On the other hand, FIG. 1B shows a wafer W′ that is misaligned when it is transferred to the exposure apparatus. In this case, the relative angular position of the wafer W′ deviates from the correct orientation by an angle θ.
In the case of the misaligned wafer W′ as shown in FIG. 1B, an operator needs to manipulate the exposure apparatus so that the detection unit P finds the alignment mark W1. That is, an additional alignment process needs to be performed when the wafer W′ is still misaligned after the first alignment process. Accordingly, the conventional alignment process may require a rather large amount of time to complete, especially with respect to a lot of wafers and thus, can be characterized as a low yield process.